This invention relates to an integrated circuit device for writing and reading information, which device includes nonvolatile memory elements and a control circuit employing complementary insulated-gate type field effect transistors.
Insulated-gate type field effect transistors which have a SAMOS structure or a MNOS structure are well-known as nonvolatile memory elements. A large number of memory elements of these kinds are integrated on a semiconductor substrate in matrix format. A "1" or "0" is selectively written into each of the memory elements and is read out from the same by a control circuit formed therearound. It is preferable that such integrated memory circuits have a minimum power consumption in order to suppress heat production.
An integrated circuit device with a control circuit of complementary insulated-gate type field effect transistors (CMOS devices) for controlling non-volatile memory arrays, which may satisfy the above requirement, is disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, No. 5, OCTOBER 1978, PP. 677-680.
As shown in the above article, known complementary insulated-gate type field effect transistors (CMOS devices) comprise an N-type semiconductor substrate, a P-type well region formed in the substrate, an N-channel MOS transistor formed on the well region and a P-channel MOS transistor formed on the substrate; wherein the gate electrodes of the N-channel and P-channel transistors are connected together, thereby constituting an input terminal. The drain regions of both transistors are connected together, thereby constituting an output terminal. When a predetermined voltage is applied between the source regions of both transistors, the CMOS device operates as an inverter.
The above-mentioned CMOS device has essentially a PNPN structure comprising the source of the P-channel MOS transistor, the N-type semiconductor substrate, the P-type well region and the source of the N-channel MOS transistor. It is possible for the PNPN structure to work as a thyristor. If so, then a circuit between the sources of the two transistors is short-circuited due to a noise signal being introduced into the PNPN structure, so that the control circuit of the CMOS devices may cause an errant behavior or may be broken in the worst case. This phenomenon, wherein a parasitic thyristor is wrongly turned on, is called "latch-up." This latch-up phenomenon can be essentially caused also in a case wherein both non-volatile memory elements and CMOS devices are formed together on the same semiconductor substrate.
Prevention of the latch-up phenomenon of CMOS devices is discussed in DENSHI TSUSHIN GAKKAI RONBUNSHI Vol. J61-C, Nov. 2, 1978, PP. 106-113. In this article, the following countermeasures for the latch-up phenomenon are shown. One of the countermeasures is to isolate electrically the P-channel MOS transistors and the N-channel MOS transistors by forming insulator layers therebetween. Another of the countermeasures is to cut off electric channels between the P-channel MOS transistors and the P-type well regions by forming P-type regions of a low impurity concentration therebetween.
Yet another of the countermeasures is to determine the mutual positional relation between the P-channel transistors and the N-channel transistors in order to prevent thyristor action of the CMOS devices. Yet another of the countermeasures is to determine the electric characteristics of the N-channel and P-channel transistors so as to prevent thyristor action of the CMOS devices. However these countermeasures bring inevitably lower integration density, more complicated manufacturing processes or deteriorated performance of the CMOS devices as inverters.